Table 8 Speedup in popular first-order masking schemes on an Cortex-M4 using simulator
From: A secure and highly efficient first-order masking scheme for AES linear operations
Scheme | Linear Operations | First-Order Security | GF256MUL21 | Time [us] | Speedup2 |
|---|---|---|---|---|---|
Unprotected AES | Original Implementation | No | Computation | 3.178 | – |
| Â | Â | Â | LUT | 14,683 | Â |
| Â | Improved Implementation | No | Computation | 14,116 | Â |
| Â | Â | Â | LUT | 0.362 | Â |
SP | Original Implementation | No | Computation | 25,177 | – |
| Â | Â | Â | LUT | 18,661 | Â |
| Â | Improved Implementation | No | Computation | 21,001 | Â |
| Â | Â | Â | LUT | 17,959 | Â |
| Â | Our Proposal | Yes | Computation | 22,909 | Â |
| Â | Â | Â | LUT | 18,922 | Â |
ASCAD | Original Implementation | Yes | Computation | 41,894 | – |
| Â | Â | Â | LUT | 28,862 | Â |
| Â | Improved Implementation | Yes | Computation | 33,542 | Â |
| Â | Â | Â | LUT | 27,458 | Â |
| Â | Our Proposal | Yes | Computation | 28,214 | 18.88% |
| Â | Â | Â | LUT | 24,056 | 14.14% |
RSMv1 | Original Implementation | No | Computation | 45,048 | – |
| Â | Â | Â | LUT | 32,016 | Â |
| Â | Improved Implementation | No | Computation | 36,696 | Â |
| Â | Â | Â | LUT | 30,612 | Â |
| Â | Our Proposal | Yes | Computation | 31,368 | Â |
| Â | Â | Â | LUT | 27,210 | Â |
RSMv2 | Original Implementation | Yes | Computation | 46,995 | – |
| Â | Â | Â | LUT | 33,963 | Â |
| Â | Improved Implementation | Yes | Computation | 38,643 | Â |
| Â | Â | Â | LUT | 32,559 | Â |
| Â | Our Proposal | Yes | Computation | 33,315 | 15.99% |
| Â | Â | Â | LUT | 29,157 | 11.67% |
| Â | More Efficient Proposal | Yes | Computation | 33,279 | 16.12% |
| Â | Â | Â | LUT | 29,148 | 11.70% |