Table 5 Speedup on an ATmeaga 163 micro-processor running at 8MHz
From: A secure and highly efficient first-order masking scheme for AES linear operations
Number of cycles | Â | Speedup |
|---|---|---|
RSMv2 | Our Proposal | Â |
27,001 | 21,287 | 26.84% |
From: A secure and highly efficient first-order masking scheme for AES linear operations
Number of cycles | Â | Speedup |
|---|---|---|
RSMv2 | Our Proposal | Â |
27,001 | 21,287 | 26.84% |