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Cybersecurity

Table 5 Comparison of implementation schemes of the MK-3 S-box

From: A circuit area optimization of MK-3 S-box

Logic gate

NOT

AND

XOR

XNOR

OR

SMIC130nm

SMIC65nm

Nangate 45nm

Reference (Wood et al. 2015)

0

144

1238

0

0

3076.06

3001.50

2667.52

This paper

0

245

411

9

6

1312.43

1321.50

1173.83

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